In the field of recording/reproducing devices, such as a magnetic disk device, and communication systems, error correction technology using error correction codes (ECC) is widely used in order to correct data error generated during recording/reproducing steps and in a transmission line.
For ECC codes, Reed Solomon (RS) codes are used (e.g. Japanese Patent Application Laid-Open No. H11-330985). In RS codes, recording data is RS-encoded in advance, bit strings reproduced after the recording/reproducing step are RS-decoded, and an error, which included the bit strings, is detected and corrected. In other words, RS codes are good in correction capability for symbol units, and are particularly excellent in detection and correction capability for burst errors.
An iterative decoding format is used as the error correction code technology. The error detection and correction capability can be improved by combining the iterative decoding and ECC. Recently, low density parity check (LDPC) codes, which is one type of iterative decoding, have seen practical use.
The LDPC codes can correct errors generated in the recording/reproducing steps by performing LDPC encoding on the recording data in advance, and performing the iterative decoding using a reliability propagation on the signals reproduced via the recording/reproducing step (e.g. Japanese Patent Application Laid-Open No. 2007-166425).
Characteristic of LDPC encoding are the linear codes that can decrease the number of “1s” (check target bit) in parity check matrix H, while increasing the code block length (that is, low density), which can be arranged at random. During LDPC decoding, an error is corrected by performing decoding using reliability propagation, which propagates the likelihood (reliability which indicates the probability of data string “0” and “1”) and decodes, and iterative decoding (decoding which iterates between a partial response channel and a reliability propagation decoder).
The LDPC encoding and decoding will now be described. Since the LDPC codes are linear codes, a parity check matrix H is generated so that the following check conditions are satisfied.wHT=0  (1)
In Expression (1), w is a code word encoded by LDPC, H is a parity check matrix, and T is a transpose of the matrix.
When the LDPC decoding is performed, the conditions to stop the iterative decoding are following two: one is that the predetermined number of times decoding was performed, and another is that the check conditions of Expression (1) that were satisfied, that is errors do not exist, and in this case, iterative decoding stops, and output is from the decoder.
Generally a log-likelihood ratio (LLR), which is a logarithmic ratio, and which is a ratio of probability that can be “0” and probability that can be “1”, is used in determining likelihood. If the original binary data is “1” positive likelihood is provided, and if “0”, negative likelihood is provided. Therefore in order to binarize the decoded data string in the iterative decoding output, binary determination can be performed using a threshold decision unit which uses “0” as the threshold.
An encoding device and a decoding device, which perform ECC correction in symbol units by combining RS codes and LDPC codes, which detect and correct an error in bit units using iterative decoding in the pre-stage of ECC, have been proposed (e.g. Japanese Patent Application Laid-Open No. 2005-093038).
Also in ECC correction, a method for improving error correction capability in a plurality of interleave systems, by combining RS codes and parity codes to detect an error, have been proposed (Toshio Itoh, Toshihiko Morita, “Error Correction Codes for 4K byte sectors”, IEEE “The Magnetic Recording Conference (TMRC 2007)”, 2007).
FIG. 15 is a diagram depicting an error correction method combining conventional RS codes and parity codes. For example, it is assumed that an encoding target is a data string formed of many blocks, of which one block is 80 bits. First each block (80 bits) is interleaved into bit spaces of 20 bits, so as to generate four blocks: 1001, 1002, 1003 and 1004. RS parities 1011, 1012, 1013 and 1014 are added to these four blocks, 1001, 1002, 1003 and 1004, by an ECC encoder respectively.
Also 2 bits of parity 1110 to 111n are calculated by a parity encoder and added to 20 bits×4 (4 blocks)=80 bits in a vertical direction. Therefore the codes generated here are configured by concatenated codes, where the horizontal direction is error correction codes based on RS codes, and the vertical direction is multi-parity (2 bit parity) error detection codes.
In this way, the blocks, divided into 4, are created by a 20-bit interleave, error correction and detection codes are created as concatenated codes, where error correction codes based on RS codes are applied in the horizontal direction of the 4 division blocks, and error detection codes based on multi-parity are applied in the vertical direction thereof.
In terms of sector data strings, an error detection code based on multi-parity is disposed at every 80 bits in a horizontal direction, so that an error can be detected in 80 bit (symbol) units, and the RS code is disposed in four 20-bit interleaves (¼ of 80 bits), so that an error can be corrected in four interleave units. Thereby, when ECC decoding fails, the correction position can be specified locally, thereby contributes to improving gain.
However, in the case of the conventional method of combining LDPC codes used for iterative decoding and RS codes used for ECC in a subsequent stage, correction capability with iterative decoding improves, but little improvement of correction capability with ECC can be expected.
On the other hand, in the case of the proposal where the conventional error correction method (ECC) concatenating RS codes and parity codes, which is based on the assumption that maximum likelihood decoding is used, error correction capability for decoding is not high.